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What's the difference between delayed branch and branch prediction?

I’m studying how delayed branch works and I’m trying to distinguish delayed branch from branch prediction. What is the difference? Is delayed branch a means to facilitate a control hazard?

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Is the registry file made from SRAM?

I study computer engineering and I read Hennessy’s book about Computer Organization where it’s described how the microprocessor does pipelining and that the microproceossor has on-chip cache, as much...

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Trouble on understanding ALU 2-bit design

I’m new to this site and I’m pretty “noobish” to electrical engineering coming from a software engineering background I was hoping someone could help me understand this design a bit. I’ve highlighted...

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How is the zero flag set in terms of hardware?

This question already has an answer here: How to find out if a binary number is zero 5 answers

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How can I connect this ram-ish memory layout

In the picture on the web, I want to connect the two inverters that are ringing around each other, I want to connect them to the data-line. I can’t seem to figure out how to properly connect them in...

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Help with harder version of carry chain adder?

I am designing an addr circuit given cin = 0, given a nand of the operands i want to add, their xor, and nor. I have drawn it in a software but i am not getting the right output, i have tried to invert...

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Curious how does ALU addressing work like in Assembly code?

When writing assembly code, say R1 = R2 + R3, it is pretty easy to understand the addressing procedure because all registers are close to the ALU. But I find it hard to see how does the ALU go to the...

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Implementing Integer Division in hardware

I am trying to figure out how to create an efficient way to divide 5 bit numbers in hardware (using registers, Shift Registers, Comparators, Muxes, basic logic gates, bit shifters, bit extenders, and...

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Why are 11, 111, 1111, … equivalent to -1 in two's complement? [duplicate]

This question already has an answer here: Binary number 11 represents? 3 answers Why All 1's used as a second input in decrement operation of ALU? 3 answers

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Is there any difference between using a decoder for the alu op code vs using...

I am a programming student studying electrical engineering fundamentals on the side. I have come across two different methods for getting the result of an operation onto the bus. A decoder accepts the...

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Why does my ALU design delay outputting the results for two clock cycles...

Hello EE StackExchange! I have been trying to design a simple 8-bit CPU for several months now. However, I am experiencing a problem: The ALU outputs the result of the operation two clock cycles after...

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Design an ALU that only adds

I need some help designing a simple ALU that only can add (4-bit) numbers. For the design I can only use 4-bit full adders and 4-bit edge-triggered flip-flops. I am stuck as I do not even know where to...

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How does this reverse NOT gate work?

I created a 74LS181 circuit in Logisim based on TI’s datasheet. Notice how the NOT gate for the B0 input has a dot before the triangle: Here’s a screenshot of my circuit: Notice that my inversion for...

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Deisgn a register file [closed]

I have a semester project to write a register file design which can support pipe-lining in hardware for alu operations?. I didn’t get much information on internet . Please share links if any useful...

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Eight bit ALU with Overflow in Verilog

I have the above assignment and here’s what I have so far in verilog: module eightbit_palu(input [7:0]a, input [7:0]b, input [1:0]sel, output [7:0]f, output ovf); reg (f, ovf); always @ (a, b, sel);...

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